This invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to the improvements of the base and emitter regions, the base leading electrode and the emitter leading electrode of a high speed, and high frequency bipolar transistor.
The recent intensive efforts to improve the performances of the bipolar transistor operating at high frequency or at high speed are found in the microfabrication technique and the self-aligning technique, which are both for reducing the parasitic capacitance possibly existing between the emitter and base, and between the base and collector, and for reducing the base resistance. In recent transistors, a polysilicon layer is used to form the base leading electrode and the emitter leading electrode, and an emitter region diffusing source. Those recent transistors are, for example, SST (super self-aligned process technology) transistors, self-aligned transistors fabricated by using RIE (reactive ion etching) technique, PSA (polysilicon self-aligned) transistors, APSA (advanced PSA) transistors, BEST (base emitter self-aligned technology) transistors, and SICOS (sidewall base contact structure) transistors. The SST transistor is fabricated through a sequence of process steps shown in FIGS. 1A to 1D. In the figure, reference symbols 101a to 101c designate SiO.sub.2 layers; 102a and 102b SiO.sub.2 layers; 103B a polysilicon layer doped with boron; 103As a polysilicon layer doped with arsenic; 104E an emitter electrode; 104B a base electrode; 104C a collector electrode. A base leading electrode is formed by polysilicon layer 103B. An emitter leading electrode is formed by polysilicon layer 103As. Polysilicon layer 103As is also used as an impurity diffusing source to form emitter region 105E. Reference symbol 105B represents a base region and 105C a collector region.
The self-aligned transistor, which is manufactured using the RIE technique, is manufactured through the process steps shown in FIGS. 2A and 2B. In the figures, reference symbols 113B is indicative of a polysilicon layer doped with boron, and reference numeral 111 designates a SiO.sub.2 layer formed by the CVD (chemical vapor deposition) process. A mask with a predetermined pattern (not shown) made of photo resist is formed on the CVD SiO.sub.2 layer 111. SiO.sub.2 layer 111 and polysilicon layer 113B are partially etched away by RIE process to form a hole which communicates with the region of the substrate where the emitter is to be formed. Then, the side portion of polysilicon layer 113B is etched by an etching solution of HF : HNO.sub.3 : CH.sub.3 COOH=1 : 3 : 8. Following the etching, the surface layer of the structure is oxidized and SiO.sub.2 layer 111 is partially etched away by RIE process to form a hole which communicates with the emitter forming region. Reference symbol 106 denotes an SiO.sub.2 layer, and reference symbol 107 denotes a base region.
In FIG. 3 showing a PSA transistor as an example of the self-aligned transistor with a polysilicon layer, polysilicon layer 123B forms a base region leading electrode. Polysilicon layer 123E forms an emitter region leading electrode, and polysilicon layer 123C forms a collector region leading electrode. Polysilicon layers 123E and 123C are also used as diffusing sources for forming emitter region 125E and collector region 125C by doping the emitter and collector regions with impurity. In other words, emitter region 125E and collector region 125C are formed by the self-align method, using the polysilicon layers 125E and 125C to reduce the transistor area. Reference symbols 125B, 125E, and 125C denote a base region leading electrode, an emitter region leading electrode, and a collector region leading electrode, respectively.
An APSA transistor, which is the PSA transistor improved to operate at a high speed, is shown in FIG. 4. As shown, as in the case of the PSA transistor, the base leading electrode made of polysilicon layer 133B is extended from that portion 135B of the P base region, which is around emitter region 135E (as viewed from the top or bottom in the drawing). An emitter contact opening and a base contact opening are formed by using a mask (not shown). Reference symbols 134E, 134B and 134C are representative of emitter, base, and collector electrode layers, respectively.
The BEST transistor is formed through a manufacturing process shown in FIGS. 5A and 5B. In the process, when the surface region of polysilicon layer 143 formed on oxide layer 146 for separating individual elements is oxidized by using Si.sub.3 N.sub.4 layer 142, the positions of the emitter contact opening and the base contact opening are defined. Reference symbols 105B, 105E, and 105C denote a base electrode, an emitter electrode, and a collector electrode, respectively.
In the SICOS transistor, the base leading electrode of the polysilicon extends from the side wall of the base region 155B, as shown in FIGS. 6A to 6D. In the manufacture thereof, an epitaxial growth layer is formed on silicon substrate 150. Further layered on the epitaxial growth layer are first SiO.sub.2 layer 151a, first Si.sub.3 N.sub.4 layer 152a, boron doped polysilicon layer 153, second Si.sub.3 N.sub.4 layer 152b, and second SiO.sub.2 layer 151b. The multilayer is dry-etched, except the portion where emitter region 155E is to be formed. The epitaxial growth layer and the multilayer are further subjected to the etching to remove the side portion thereof (FIG. 6A). Then, the structure is oxidized to form a Si.sub.3 N.sub.4 layer (not shown) on the surface region of the structure. Thereafter, the structure is subjected to the dry etching process to remove that portion of the Si.sub.3 N.sub.4 layer which is on the epitaxial layer. Further, it is subjected to the selective oxidation to form a thick SiO.sub.2 layer on the epitaxial layer. Succeedingly, that portion of the Si.sub.3 N.sub.4 layer which is on the side wall of the multilayer is removed. Thereafter, impurity doped polysilicon layer 163 is formed over the entire surface of the structure, and is patterned to form base leading electrode. Reference symbols 155E and 155C denote an emitter electrode, and a collector electrode, respectively.
As described above, transistors other than the PSA and APSA transistors are manufactured using the RIE technique, which is complicated and instable. This indicates a low yield of these transistors. In the case of the SST transistor, since the self-align process is frequently used, the number of masks used in the process from the formation of base region 105B to the formation of emitter region 105E is very small, only 2, when comparing with that (4 to 5) of the general bipolar transistor. In this respect, the number of formations of the resist pattern is reduced to improve the cost performance. However, the self-align technique involves one problem to be solved. In FIG. 7, this problem resides in the formation of base leading electrode 173B and emitter region 175E, and in the formation of insulating layer 171 for insulating emitter leading electrode 173E from base leading electrode 173B. The formation of this insulating layer 171 is very complicated in such a way that base leading electrode 173B is partially oxidized or a CVD-SiO.sub.2 layer is formed, and it is processed by the RIE technique to remain that portion 171a thereof which is on the side wall of base leading electrode 173B.
In FIG. 7, reference symbol 175E designates an emitter region, and 175B and 177 base regions, and 176 an SiO.sub.2 layer.
As described above, the prior art semiconductor device and its manufacturing method can provide almost satisfactory electrical characteristics, but need many masks during manufacturing. Use of many masks makes the manufacturing process complicated and the resultant products more expensive.